A phase lock loop (PLL) is a circuit used to synthesize a "clean" output signal based on an input reference signal that may be noisy and jittery. The output signal will have the same long-term frequency and phase as the input signal.
The components of a typical PLL include an input reference signal, which displays a level of noise and jitter that may be unacceptable. A voltage controlled oscillator (VCO) is used to produce the PLL output signal. The input reference signal and the PLL output signal, which is carried by a feedback loop from the VCO output, are input to a phase detector which produces an error signal indicating the magnitude of the phase difference between the input reference signal and the PLL output signal. The phase error signal is integrated through a phase lock loop filter and input as a control signal to the VCO. This control signal causes the phase of the VCO output signal to converge on the phase of the input reference signal, thus minimizing the phase error.
In designing a PLL for a specific application, a decision must be made regarding the value of the bandwidth of the phase lock loop filter. A low-pass filter with a higher bandwidth will cause the VCO output signal to converge on the input reference signal more rapidly. However, the low-pass filter will be more sensitive to fluctuations in phase and frequency, and thus cause the VCO output signal to exhibit a larger degree of instability. A low-pass filter with a lower bandwidth will cause the VCO output signal to exhibit a larger degree of long-term stability, but the PLL will take longer to converge on the input reference signal when fluctuations in phase and frequency are present.
Therefore, it is desirable to have functionality incorporated into a PLL that will automatically select among a set of available phase lock loop filters the one that, for the instant situation, will most rapidly bring the VCO output signal into convergence with the input reference signal.
In the field of the present invention, i.e., digital PLLs, a known solution to providing functionality to select an appropriate phase lock loop filter is a microprocessor-controlled digital phase lock detector that determines the magnitude of the phase error and adjusts the bandwidth of the loop filter. However, a microprocessor and the firmware required to control the PLL can be too expensive a solution.
Accordingly, it is an object of the present invention to provide a relatively inexpensive circuit in hardware for use in analog or digital PLLs that will automatically generate a phase lock loop filter selection signal that is based on the magnitude of the phase error between an input reference signal and the VCO output signal.